Interconnect-Centric SoC Design for Network-on-Chip

The system-on-chip (SoC) design paradigm and deep submicron (DSM) technology bring two main challenges to the ASIC design community. The first one is productivity to use millions of gates within ever shorter time-to-market, which is currently tackled with the design methodology based on Intellectual Property Right (IPR) blocks. The second challenge is coping with rapidly changed technology parameters, where interconnect invites many signal and power integrity related problems. It is now clear that in ultra-deep submicron SoC design, interconnect will be a main design constraint and dominating effects in terms of system architecture, performance, robustness, power consumption, and cost. As an example, our study revealed that in a 0.07μm CMOS chip, unless the system cock rate is greatly reduced otherwise, the maximum region that can be synchronized is about 6mm due to excessive interconnect delay and crosstalk [1]. Thus, new models and templates for design architectures are needed. One of such strongly emerging approaches is network-on-chip (NoC) based architectures and platforms. In NoC, global interconnects are reserved for global communications. Consequently, the maximum synchronous region would be just 3 mm due to the interconnect limitation. Therefore, in future SoC design, issues of interconnect constraints must be accurately addressed in early system decisions and performance analysis in all abstraction levels and in different phases of the design refinement process. Interconnects are no longer separate post-layout and back-annotated issues, but are up-front system and architecture design issues. We need to describe the necessary physical properties and constraints in as attributes to interconnect library or interconnect IPRs. Only when these “virtual wires” are integrated in analyses, decisions made at high levels will be accurate; rework and iterations between system design and physical design will be reduced.